1. Field of the Invention
The present invention relates to a trench isolation method for manufacturing a semiconductor integrated circuit.
2. Description of the Related Art
As the integration density of integrated circuits increases, the technology for forming an isolation region between the active regions becomes important. Trench isolation methods are widely employed for this purpose. In these methods, a trench is formed by etching at a predetermined area of a semiconductor substrate, and then the trench is filled with an insulating material. This increases the effective distance between adjacent transistors in active regions. The area of the isolation region is kept at a minimum by designing the trench to be deep and narrow. This is why the insulating material inside the trench is also called insulating film.
A prior art trench isolation method is now described with reference to FIGS. 1 through 3. Referring to FIG. 1, a pad oxide film, a pad nitride film, and a chemical vapor deposition (CVD) oxide film are sequentially formed on a semiconductor substrate 1. A pad oxide film pattern 3, a pad nitride film pattern 5, and a CVD oxide film pattern 7 for exposing a predetermined area of the semiconductor substrate 1 are formed by continuously patterning the CVD oxide film, the pad nitride film, and the pad oxide film. A trench T is formed by etching exposed semiconductor substrate 1 using CVD oxide film pattern 7 as an etching mask.
Referring to FIG. 2, an insulating material filling the trench T is deposited on the entire surface of the resultant structure where the trench T is formed. The entire surface of the insulating film is etched until pad nitride film pattern 5 is exposed. A CMP process is widely used for this purpose. The insulating film has been formed into an insulating film pattern 9.
Referring to FIG. 3, exposed pad nitride film pattern 5 and pad oxide film pattern 3 are removed. This exposes the active region of the substrate around the trench for further processing. Then insulating film pattern 9 is etched, forming an isolating film 9a that has a recessed groove at an edge A.
The recessed groove exposes an upper comer of the trench accordingly, when a MOS transistor is later formed near the trench, a gate electric field caused by a gate voltage applied between a gate electrode of the MOS transistor and the substrate becomes disproportionately concentrated on the upper comer of the trench. As a result, even though a sub-threshold voltage is being applied to the gate electrode, a channel is nevertheless formed on a side wall of the trench. Accordingly, leakage current flows between a source area and a drain area of the MOS transistor. This phenomenon often occurs in MOS transistors having a narrow channel width. Also, the high concentration of electric field at the upper comer of the trench deteriorates the reliability of a gate oxide film.